ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 226

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Operating Modes
must send this repeated START condition or STOP condition at the same position in the
format frame. In other words, arbitration is not allowed between:
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•
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Clock Synchronization for Handshake
The clock-synchronizing mechanism functions as a handshake, enabling receivers to cope
with fast data transfers, on either a byte or a bit level. The byte level allows a device to
receive a byte of data at a fast rate, but allows the device more time to store the received
byte or to prepare another byte for transmission. Slaves hold the SCL line Low after recep-
tion and acknowledge the byte, forcing the master into a Wait state until the slave is ready
for the next byte transfer in a handshake procedure.
Master Transmit
In MASTER TRANSMIT mode, the I
Enter MASTER TRANSMIT mode by setting the STA bit in the I2C_CTL register to 1.
The I
When a START condition is transmitted, the IFLG bit is 1 and the status code in the
I2C_SR register is
loaded with either a 7-bit slave address or the first part of a 10-bit slave address, with the
lsb cleared to 0 to specify TRANSMIT mode. The IFLG bit must now be cleared to 0 to
prompt the transfer to continue.
After the 7-bit slave address (or the first part of a 10-bit address) plus the Write bit are
transmitted, the IFLG is set again. A number of status codes are possible in the I2C_SR
register. See
A repeated START condition and a data bit.
A STOP condition and a data bit.
A repeated START condition and a STOP condition.
2
C then tests the I
Table 118
08h
2
. Before this interrupt is serviced, the I2C_DR register must be
on page 219.
C bus and transmits a START condition when the bus is free.
2
C transmits a number of bytes to a slave receiver.
Product Specification
I
2
C Serial I/O Interface
eZ80F91 ASSP
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