ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 334

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 213. EMAC Receive Read Pointer Register—High Byte
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read Only, R/W = Read/Write
Bit
Position
[7:0]
EMAC_RRP_H
EMAC Buffer Size Register
The lower six bits of this register set the level at which the EMAC either transmits a pause
control frame or jams the Ethernet bus, depending on the mode selected. When each of
these bits contain a zero, this feature is disabled.
In FULL-DUPLEX mode, a Pause Control Frame is transmitted as a One-shot operation.
The software must free up a number of Rx buffers so that the number of buffers remaining,
EmacBlksLeft, is greater than TCPF_LEV.
In HALF-DUPLEX mode, the EMAC jams the Ethernet by sending a continuous stream
of hexadecimal 5s (
buffers remaining, EmacBlksLeft, is greater than TCPF_LEV, the EMAC stops jamming.
Value
00h–FFh These bits represent the High byte of the 2-byte EMAC
R
7
0
Description
Receive Read Pointer value, {EMAC_RRP_H,
EMAC_RRP_L}. Bit 7 is bit 15 (msb) of the 16-bit value. Bits
7:5 default to 000 on reset; bit 0 is bit 8 of the 16-bit value.
R
5fh
6
0
). When the software frees up the Rx buffers and the number of
R
5
0
R/W
4
0
R/W
3
0
R/W
2
0
(EMAC_RRP_H = 004Ah)
R/W
Ethernet Media Access Controller
1
0
Product Specification
R/W
0
0
eZ80F91 ASSP
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