ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 95

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 29. Chip Select x Control Register (CS0_CTL = 00AAh, CS1_CTL = 00ADh,
CS2_CTL = 00B0h, CS3_CTL = 00B3h)
PS027001-0707
Bit
CS0_CTL Reset
CS1_CTL Reset
CS2_CTL Reset
CS3_CTL Reset
CPU Access
Note: R/W = Read/Write; R = Read Only.
Bit
Position
[7:5]
CSX_WAIT
4
CSX_IO
3
CSX_EN
[2:0]
Chip Select x Control Register
The Chip Select x Control register (see
type of chip select, and sets the number of wait states. The reset state for the Chip Select 0
Control register is
00h
Value Description
000
001
010
011
100
101
110
111
0
1
0
1
000
.
R/W
0 wait states are asserted when this chip select is active.
1 wait state is asserted when this chip select is active.
2 wait states are asserted when this chip select is active.
3 wait states are asserted when this chip select is active.
4 wait states are asserted when this chip select is active.
5 wait states are asserted when this chip select is active.
6 wait states are asserted when this chip select is active.
7 wait states are asserted when this chip select is active.
Chip select is configured as a memory chip select.
Chip select is configured as an I/O chip select.
Chip select is disabled.
Chip select is enabled.
Reserved.
7
1
0
0
0
R/W
E8h
6
1
0
0
0
when the reset state for the 3 other Chip Select Control registers is
R/W
5
1
0
0
0
R/W
4
0
0
0
0
Table
R/W
3
1
0
0
0
29) enables the chip selects, specifies the
R
2
0
0
0
0
R
1
0
0
0
0
Chip Selects and Wait States
Product Specification
R
0
0
0
0
0
eZ80F91 ASSP
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