ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 200

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 106. UART Line Status Registers
PS027001-0707
Bit
Position
1
RTS
0
DTR
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
7
ERR
6
TEMT
5
THRE
UART Line Status Register
This register is used to show the status of UART interrupts and registers. See
Value
0–1
0–1
Value
0
1
0
1
0
1
Description
Request to Send
In normal operation, the RTS output port is the inverse of this
bit. In LOOP BACK mode, this bit is connected to the CTS bit in
the UART Status Register.
Data Terminal Ready.
In normal operation, the DTR output port is the inverse of this
bit. In LOOP BACK mode, this bit is connected to the DSR bit
in the UART Status Register.
Description
Always 0 when operating in with the FIFO disabled. With the
FIFO enabled, this bit is reset when the UARTx_LSR register is
read and there are no more bytes with error status in the FIFO.
Error detected in the FIFO. There is at least 1 parity, framing or
break indication error in the FIFO.
Transmit holding register/FIFO is not empty or transmit shift
register is not empty or transmitter is not idle.
Transmit holding register/FIFO and transmit shift register are
empty; and the transmitter is idle. This bit cannot be set to 1
during the BREAK condition. This bit only becomes 1 after the
BREAK command is removed.
Transmit holding register/FIFO is not empty.
Transmit holding register/FIFO. This bit cannot be set to 1
during the BREAK condition. This bit only becomes 1 after the
BREAK command is removed.
R
7
0
R
6
1
R
5
1
(UART0_LSR = 00C5h, UART1_LSR = 00 D5h)
R
4
0
R
3
0
Universal Asynchronous Receiver/Transmitter
R
2
0
R
1
0
Product Specification
R
0
0
eZ80F91 ASSP
Table
106.
192