ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 93

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 27. Chip Select x Lower Bound Register
CS2_LBR = 00AEh, CS3_LBR = 00B1h)
PS027001-0707
Bit
CS0_LBR Reset
CS1_LBR Reset
CS2_LBR Reset
CS3_LBR Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
CSX_LBR
Chip Select Registers
Value Description
00h–
FFh
Chip Select x Lower Bound Register
For Memory chip selects, the chip select x Lower Bound register (see
the lower bound of the address range for which the corresponding Memory chip select (if
enabled) is active. For I/O chip selects, the chip select x Lower Bound register defines the
address to which ADDR[15:8] is compared to generate an I/O chip select. All chip select
lower bound registers reset to
For Memory Chip Selects (CSx_IO = 0)
This byte specifies the lower bound of the chip select address
range. The upper byte of the address bus, ADDR[23:16], is
compared to the values contained in these registers for
determining whether a Memory chip select signal must be
generated.
For I/O Chip Selects (CSx_IO = 1)
This byte specifies the chip select address value. ADDR[15:8] is
compared to the values contained in these registers for
determining whether an I/O chip select signal must be generated.
R/W
7
0
0
0
0
R/W
6
0
0
0
0
R/W
5
0
0
0
0
00h
.
R/W
4
0
0
0
0
(CS0_LBR = 00A8h, CS1_LBR = 00ABh,
R/W
3
0
0
0
0
R/W
2
0
0
0
0
R/W
1
0
0
0
0
Chip Selects and Wait States
Product Specification
R/W
0
0
0
0
0
Table
eZ80F91 ASSP
27) defines
85