ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 9

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Architectural Overview
PS027001-0707
Features
Zilog’s eZ80F91 device is a member of Zilog’s family of eZ80AcclaimPlus!™ Flash
ASSPs. The eZ80F91 is an high-speed ASSP with a maximum clock speed of 50 MHz
and single-cycle instruction fetch. It operates in Z80
makes it suitable for a variety of applications, including industrial control, embedded
communication, and point-of-sale terminals.
eZ80F91 device includes the following features:
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KB) or full 24-bit addressing mode (16 MB). The rich peripheral set of the eZ80F91
Single-cycle instruction fetch, high-performance, pipelined eZ80
(referred as The CPU in this document)
10/100 BaseT ethernet media access controller with Media-Independent
Interface (MII)
256 KB Flash memory
16 KB SRAM (8 KB user and 8 KB Ethernet)
Low-power features including SLEEP mode, HALT mode, and selective peripheral
power-down control
Two Universal Asynchronous Receiver/Transmitter (UART) with independent Baud
Rate Generators (BRG)
Serial Peripheral Interface (SPI) with independent clock rate generator
I
IrDA-compliant infrared encoder/decoder
Glueless external peripheral interface with 4 Chip Selects, individual Wait State
generators, an external WAIT input pin—supports Z80-, Intel-, and Motorola-style
buses
Fixed-priority vectored interrupts (both internal and external) and interrupt controller
Real-time clock with separate V
32 kHz oscillator or external 50/60 Hz input
Four 16-bit Counter/Timers with prescalers and direct input/output drive
Watchdog Timer with internal oscillator clocking option
32 bits of General Purpose Input/Output (GPIO)
On-Chip Instrumentation (OCI™) and Zilog Debug Interfaces (ZDI)
2
C with independent clock rate generator
DD
pin for battery backup and selectable on-chip
®
-compatible addressing mode (64
Product Specification
®
Architectural Overview
CPU core
eZ80F91 ASSP
1