ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 220

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 116. SPI Transmit Shift Register (SPI_TSR = 00BCh)
Table 117. SPI Receive Buffer Register
PS027001-0707
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
[7:0]
TX_DATA
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
[7:0]
RX_DATA
SPI Receive Buffer Register
The SPI Receive Buffer register (SPI_RBR) is used by the SPI slave to receive data from
the serial bus. The SPIF bit must be cleared prior to a second transfer of data from the shift
register; otherwise, an overrun condition exists. In the event of an overrun, the byte that
causes the overrun is lost.
The SPI Receive Buffer Read Only register shares the same address space as the SPI
Transmit Shift Write Only register. See
Value
00h–FFh SPI transmit data.
Value
00h–FFh
W
X
X
R
7
7
Description
Description
SPI received data.
W
X
X
R
6
6
W
X
X
R
5
5
(SPI_RBR = 00BCh)
W
X
X
R
4
4
Table
W
R
X
X
3
3
117.
W
R
X
X
2
2
W
R
X
X
1
1
Product Specification
Serial Peripheral Interface
W
R
X
X
0
0
eZ80F91 ASSP
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