ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 240

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 130. I
PS027001-0707
Bit
Reset
CPU Access
Note: W = Read only.
Bit
Position
7
[6:3]
M
[2:0]
N
2
C Clock Control Registers
I
The I
which the I
is in MASTER mode. The Write Only I
the Read Only I2C_SR registers. See
The I
of this system clock is f
f
In MASTER mode, the I
lowing equation:
The use of two separately-programmable dividers allows the MASTER mode output
frequency to be set independently of the frequency at which the I
feature is particularly useful in multimaster systems because the frequency at which the
I
to ensure that START and STOP conditions are always detected. By using two
2
SAMP
2
C Clock Control Register
C bus is sampled must be at least 10 times the frequency of the fastest master on the bus
Value
0
0000–1111 I
000–111
2
2
f
f
C_CCR register is a Write Only register. The seven LSBs control the frequency at
C clocks are derived from the system clock of the eZ80F91 device. The frequency
SAMP
SCL
supplied by the following equation:
2
W
=
7
0
C bus is sampled and the frequency of the I
=
10 • (M + 1)(2)
Description
Reserved.
I
2
2
f
C clock divider scalar value.
C clock divider exponent.
SCLK
2
W
6
0
N
f
SCLK
SCK
2
C clock output frequency on SCL (f
. The I
W
5
0
(I2C_CCR = 00CCh)
N
2
C bus is sampled by the I
W
4
0
Table
2
C_CCR registers share the same I/O addresses as
130.
W
3
0
W
2
0
2
C clock line (SCL) when the I
W
2
1
0
C block at the frequency
SCL
Product Specification
2
) is supplied by the fol-
C bus is sampled. This
W
0
0
I
2
C Serial I/O Interface
eZ80F91 ASSP
2
C
232