ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 331

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 207. EMAC Boundary Pointer Register—Low Byte
Table 208. EMAC Boundary Pointer Register—High Byte
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read Only, R/W = Read/Write.
Bit
Position
[7:0]
EMAC_BP_L
Bit
Reset
CPU Access
Note: R = Read Only, R/W = Read/Write.
Bit
Position
[7:0]
EMAC_BP_H
EMAC Boundary Pointer Register—Low and High Bytes
The Boundary Pointer is set to the start of the Receive buffer (end of Transmit buffer +1)
in EMAC shared memory. This pointer is 24 bits and determined by {RAM_ADDR_U,
EMAC_BP_H, EMAC_BP_L}. The upper 3 bits of the EMAC_BP_H register are hard-
wired inside the eZ80F91 device to locate the base of EMAC shared memory. The last 5
bits of the EMAC_BP_L register value are hard-wired to keep the addressing aligned to
a 32 byte boundary. See
EMAC Boundary Pointer Register—Upper Byte
The EMAC Boundary Pointer Register maps directly to the RAM_ADDR_U register
within the eZ80F91 device. This register value is Read Only. See
Value
00h–FFh These bits represent the Low byte of the 3 byte EMAC
Value
00h–FFh These bits represent the High byte of the 3 byte EMAC
R/W
Description
Boundary Pointer value, {EMAC_BP_U, EMAC_BP_H,
EMAC_BP_L}. Bit 7 is bit 15 of the 24 bit value. Bit 0 is bit 8 of
the 24 bit value.
Description
Boundary Pointer value, {EMAC_BP_U, EMAC_BP_H,
EMAC_BP_L}. Bit 7 is bit 7 of the 24 bit value. Bit 0 is bit 0 of
the 24 bit value.
R
7
0
1
15:13
R/W
R
6
0
1
Table 207
R/W
R
5
0
0
R/W
and
R
4
0
0
Table
R/W
R
3
0
0
208.
(EMAC_BP_L = 0044h)
(EMAC_BP_H = 0045h)
12:8
R/W
R
2
0
0
R/W
Ethernet Media Access Controller
R
1
0
0
Product Specification
Table 209
R/W
R
0
0
0
eZ80F91 ASSP
on page 324.
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