ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 153

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Multi-PWM Mode
Timer Output Compare Value Register—High Byte
The Timer3 Output Compare x Value Register—High Byte (see
byte of the compare value for OC0–OC3.
Table 69. Compare Value Register—High Byte
TMR3_OC1_H = 0085h, TMR3_OC2_H = 0087h, TMR3_OC3_H = 0089h)
The special Multi-PWM mode uses the Timer 3 16-bit counter as the primary timekeeper
to control up to 4 PWM generators. The 16-bit reload value for Timer 3 sets a common
period for each of the PWM signals. However, the duty cycle and phase for each generator
are independent that is, the High and Low periods for each PWM generator are set inde-
pendently. In addition, each of the 4 PWM generators are enabled independently.
The 8 PWM signals (4 PWM output signals and their inverses) are output via Port A. A
functional block diagram of the Multi-PWM is illustrated in
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
TMR3_OCx_H
Value
00h–FFh
R/W
7
0
Description
These bits represent the High byte of the 2-byte compare
value, {TMR3_OCx_H[7:0], TMR3_OCx_L[7:0]}. Bit 7 is bit
15 (msb) of the 16-bit data value. Bit 0 is bit 8
of the 16-bit timer compare value.
R/W
6
0
R/W
5
0
R/W
4
0
(TMR3_OC0_H = 0083h,
R/W
Figure 30
3
0
Programmable Reload Timers
Table
Product Specification
R/W
2
0
69) stores the High
on page 146.
eZ80F91 ASSP
R/W
1
0
R/W
0
0
145