ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 255

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 136. ZDI Break Control Register
Address Space)
PS027001-0707
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
7
brk_next
6
brk_addr3
5
brk_addr2
4
brk_addr1
3
brk_addr0
Value Description
0
1
0
1
0
1
0
1
0
1
W
7
0
The ZDI break on the next CPU instruction is disabled.
Clearing this bit releases the CPU from its current BREAK
condition.
The ZDI break on the next CPU instruction is enabled. The
CPU uses multibyte Op Codes and multibyte operands.
Break points only occur on the first Op Code in a multibyte
Op Code instruction. If the ZCL pin is High and the ZDA pin
is Low at the end of RESET, this bit is set to 1 and a break
occurs on the first instruction following the RESET. This bit
is set automatically during ZDI break on address match. A
break is also forced by writing a 1 to this bit.
The ZDI break, upon matching break address 3, is
disabled.
The ZDI break, upon matching break address 3, is
enabled.
The ZDI break, upon matching break address 2, is
disabled.
The ZDI break, upon matching break address 2, is
enabled.
The ZDI break, upon matching break address 1, is
disabled.
The ZDI break, upon matching break address 1, is
enabled.
The ZDI break, upon matching break address 0, is
disabled.
The ZDI break, upon matching break address 0, is
enabled.
W
6
0
W
5
0
(ZDI_BRK_CTL = 10h in the ZDI Write Only Register
W
4
0
W
3
0
W
2
0
W
1
0
Product Specification
W
0
0
Zilog Debug Interface
eZ80F91 ASSP
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