ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 18

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Table 2. Pin Identification on the eZ80F91 Device (Continued)
LQFP
Pin No
61
62
63
64
65
66
67
68
69
BGA
Pin No Symbol
M8
L8
J7
K8
M9
H7
L9
J8
K9
RTC_X
RTC_X
RTC_V
V
HALT_SLP HALT and
TMS
TCK
TRIGOUT
TDI
SS
IN
OUT
DD
Function
JTAG Test
Real-Time
Clock Crystal
Input
Real-Time
Clock Crystal
Output
Real-Time
Clock Power
Supply
Ground
SLEEP
Indicator
Mode Select
JTAG Test
Clock
JTAG Test
Trigger Output
JTAG Test
Data In
Signal Direction Description
Input
Bidirectional
Output, Active
Low
Input
Input
Output
Bidirectional
This pin is the input to the low-power
32 kHz crystal oscillator for the
Real-time clock. If the Real-time
clock is disabled or not used, this
input must be left floating or tied to
VSS to minimize any input current
leakage.
This pin is the output from the low-
power 32 kHz crystal oscillator for
the Real-Time Clock. This pin is an
input when the RTC is configured to
operate from 50/60 Hz input clock
signals and the 32 kHz crystal
oscillator is disabled.
Power supply for the Real-Time
Clock and associated 32 kHz
oscillator. Isolated from the power
supply to the remainder of the chip.
A battery is connected to this pin to
supply constant power to the Real-
Time Clock and 32 kHz oscillator. If
the Real-time clock is disabled or
not used this output must be tied to
Vdd.
Ground.
A Low on this pin indicates that the
CPU has entered either HALT or
SLEEP mode because of execution
of either a HALT or SLP instruction.
JTAG Mode Select Input.
JTAG and ZDI clock input.
Active High trigger event indicator.
JTAG data input pin. Functions as
ZDI data I/O pin when JTAG is
disabled. This pin has an internal
pull-up resistor in the pad.
Product Specification
Architectural Overview
eZ80F91 ASSP
10