ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 182

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 93. Real-Time Clock Control Register
PS027001-0707
Bit
Reset
CPU Access
Note: X = Unchanged by RESET; R = Read Only; R/W = Read/Write.
Bit Position
7
ALARM
6
INT_EN
5
BCD_EN
4
CLK_SEL
3
FREQ_SEL
2
DAY_SAV
1
SLP_WAKE
0
RTC_UNLOCK
32768. If the power-line frequency option is selected, the prescale value is set by the
FREQ_SEL bit, and the 32 kHz oscillator is disabled. See
Value Description
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Alarm interrupt is inactive.
Alarm interrupt is active.
Interrupt on alarm condition is disabled.
Interrupt on alarm condition is enabled.
RTC count and alarm value registers are binary.
RTC count and alarm value registers are BCD.
RTC clock source is crystal oscillator output (32768 Hz).
On-chip 32768Hz oscillator is enabled.
RTC clock source is power-line frequency input.
On-chip 32768 Hz oscillator is disabled.
Power-line frequency is 60 Hz.
Power-line frequency is 50 Hz.
Suggested value for Daylight Savings Time not selected.
Suggested value for Daylight Savings Time selected.
This register bit has been allocated as a storage location only
for software applications that use DST. No action is performed
in the eZ80F91 when setting or clearing this bit.
RTC did not generate a sleep-mode recovery reset.
RTC Alarm generated a sleep-mode recovery reset.
RTC count registers are locked to prevent write access.
RTC counter is enabled.
RTC count registers are unlocked to allow write access.
RTC counter is disabled.
X
R
7
R/W
6
0
R/W
X
5
R/W
(RTC_CTRL = 00EDh)
X
4
R/W
X
3
R/W
X
2
Table
0/1
R
1
Product Specification
93.
R/W
0
0
eZ80F91 ASSP
Real-Time Clock
174