ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 166

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Pulse-Width Modulation Falling Edge—Low Byte
A parallel 16-bit Write of {TMR3_PWMxF_H[7–0], TMR3_PWMxF_L[7–0]} occurs
when software initiates a Write to TMR3_PWMxF_L. The register is detailed in
Table 78. PWMx Falling-Edge Register—Low Byte
TMR3_PWM1F_L = 0086h, TMR3_PWM2F_L = 0088h, TMR3_PWM3F_L = 008Ah)
Pulse-Width Modulation Falling Edge—High Byte
Writing to TMR3_PWMxF_H stores the value in a temporary holding register. A parallel
16-bit Write of {TMR3_PWMxF_H[7–0], TMR3_PWMxF_L[7–0]} occurs when
software initiates a Write to TMR3_PWMxF_L. The register is detailed in
Table 79. PWMx Falling-Edge Register—High Byte
TMR3_PWM1F_H = 0087h, TMR3_PWM2F_H = 0089h, TMR3_PWM3F_H = 008Bh)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
PWMXF_L
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
PWMXF_H
Value
00h–FFh
Value
00h–FFh
Description
These bits represent the Low byte of the 16-bit value to set the
falling edge COMPARE value for PWMx,
{TMR3_PWMXF_H[7:0], TMR3_PWMXF_L[7:0]}. Bit 7 is bit 7
of the 16-bit timer data value. Bit 0 is bit 0 (lsb) of the
16-bit timer data value.
Description
These bits represent the High byte of the 16-bit value to set the
falling edge COMPARE value for PWMx,
{TMR3_PWMXF_H[7:0], TMR3_PWMXF_L[7:0]}. Bit 7 is bit 15
(msb) of the 16-bit timer data value. Bit 0 is bit 8 of the
16-bit timer data value.
R/W
R/W
7
0
7
0
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
R/W
R/W
4
0
4
0
R/W
R/W
(TMR3_PWM0F_L = 0084h,
(TMR3_PWM0F_H = 0085h,
3
0
3
0
Programmable Reload Timers
Product Specification
R/W
R/W
2
0
2
0
eZ80F91 ASSP
Table
R/W
R/W
1
0
1
0
Table
79.
R/W
R/W
0
0
0
0
78.
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