ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 281

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 153. PLL Divider Register—High Bytes
Table 154. PLL Control Register 0 (PLL_CTL0 = 005Eh)
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
[7:3]
[2:0]
PLL_DIV_H
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit
Position
[7:6]
CHRP_CTL1
PLL Control Register 0
The charge pump program, lock detect sensitivity, and system clock source selections are
set using this register. A brief description of each of these PLL Control Register 0
attributes is listed below, and further described in
Charge Pump Program (CHRP_CTL)—
current.
Lock Detect Sensitivity (LDS_CTL)—
System Clock Source (CLK_MUX)—
the external crystal oscillator (XTAL), PLL, or Real-Time Clock crystal oscillator.
Value Description
00
01
10
11
Value
00h
0h–7h
Charge pump current = 100 µA
Charge pump current = 500 µA
Charge pump current = 1.0 mA
Charge pump current = 1.5 mA
R/W
W
Description
Reserved
These bits represent the High byte of the 11 bit PLL divider
value. The complete PLL divider value is returned by
{PLL_DIV_H, PLL_DIV_L}.
7
0
7
0
R/W
W
6
0
6
0
W
R
5
0
5
0
W
R
4
0
4
0
(PLL_DIV_H = 005Dh)
Selects the system clock source from a choice of
Determines the lock criteria for the PLL.
Selects one of four values of charge pump
R/W
W
3
0
3
0
Table
R/W
W
2
0
2
0
154.
R/W
W
1
0
1
0
Product Specification
R/W
W
0
0
0
0
Phase-Locked Loop
eZ80F91 ASSP
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