ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 151

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Timer Output Compare Control Register 2
The Timer3 Output Compare Control Register 2 (see
that occurs on the output compare pins when a timer compare happens.
Table 67. Timer Output Compare Control Register 2
3
OC1_INIT
2
OC0_INIT
1
MAST_MODE
0
OC_EN
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:6]
OC3_MODE
[5:4]
OC2_MODE
0
1
0
1
0
1
0
1
Value
00
01
10
11
00
01
10
11
R/W
7
0
OC pin cleared when initialized.
OC pin set when initialized.
OC pin cleared when initialized.
OC pin set when initialized.
OC pins are independent.
OC pins all mimic OC0.
OUTPUT COMPARE mode is disabled.
OUTPUT COMPARE mode is enabled.
Description
Initialize OC pin to value specified in
TMR3_OC_CTL1[OC3_INT].
OC pin is cleared upon timer compare.
OC pin is set upon timer compare.
OC pin toggles upon timer compare.
Initialize OC pin to value specified in
TMR3_OC_CTL1[OC2_INT].
OC pin is cleared upon timer compare.
OC pin is set upon timer compare.
OC pin toggles upon timer compare.
R/W
6
0
R/W
5
0
R/W
4
0
Table
R/W
67) is used to select the event
3
0
(TMR3_OC_CTL2 = 0081h)
Programmable Reload Timers
Product Specification
R/W
2
0
eZ80F91 ASSP
R/W
1
0
R/W
0
0
143