ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 222

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Data Validity
The data on the SDA line must be stable during the High period of the clock. The High or
Low state of the data line changes only when the clock signal on the SCL line is Low, as
illustrated in
START and STOP Conditions
Within the I
STOP conditions.
SCL is High, indicating a START condition. A Low-to-High transition on the SDA line
while SCL is High defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered to
be busy after a START condition. The bus is considered to be free for a defined time after
a STOP condition.
SDA Signal
SCL Signal
SDA Signal
SCL Signal
2
Figure 44. START and STOP Conditions In I
C bus protocol, unique situations arise which are defined as START and
Figure
START Condition
Figure 44
Figure 43. I
43.
S
Data Valid
Data Line
Stable
illustrates a High-to-Low transition on the SDA line while
2
C Clock and Data Relationship
Data Allowed
Change of
2
Product Specification
C Protocol
STOP Condition
I
2
C Serial I/O Interface
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