ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 94

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 28. Chip Select x Upper Bound Register (CS0_UBR = 00A9h, CS1_UBR = 00ACh,
CS2_UBR = 00AFh, CS3_UBR = 00B2h)
PS027001-0707
Bit
CS0_UBR Reset
CS1_UBR Reset
CS2_UBR Reset
CS3_UBR Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
CSX_UBR
Chip Select x Upper Bound Register
For Memory chip selects, the Chip Select x Upper Bound registers, detailed in
defines the upper bound of the address range for which the corresponding Chip Select (if
enabled) are active. For I/O chip selects, this register produces no effect. The reset state for
the Chip Select 0 Upper Bound register is
Select Upper Bound registers is
Value Description
00h–
FFh
R/W
For Memory Chip Selects (CSx_IO = 0)
This byte specifies the upper bound of the chip select address
range. The upper byte of the address bus, ADDR[23:16], is
compared to the values contained in these registers for
determining whether a chip select signal must be generated.
For I/O Chip Selects (CSx_IO = 1)
No effect.
7
1
0
0
0
R/W
6
1
0
0
0
R/W
5
1
0
0
0
00h
R/W
4
1
0
0
0
.
FFh
R/W
3
1
0
0
0
when the reset state for the other Chip
R/W
2
1
0
0
0
R/W
1
1
0
0
0
Chip Selects and Wait States
Product Specification
R/W
0
1
0
0
0
eZ80F91 ASSP
Table
28,
86