ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 136

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

eZ80F91 ASSP
Product Specification
128
RTC Oscillator Input
When the timer clock source is the Real-Time Clock signal, the timer functions just as it
does in EVENT COUNT mode, except that it samples the internal RTC clock rather than
the ECx pin.
Input Capture
INPUT CAPTURE mode allows the CPU to determine the timing of specified events on a
set of external pins.
A timer intended for use in INPUT CAPTURE mode is setup the same way as in BASIC
mode, with one exception. The CPU must also write the TMRx_CAP_CTL register to
select the edge on which to capture: rising, falling, or both. When one of these events
occurs on an input capture pin, the current 16 bit timer value is latched into the capture
value register pair (TMRx_CAP_A or TMRx_CAP_B depending on the IC pin exhibiting
the event).
Reading the Low byte of the register pair causes the timer to ignore other capture events
on the associated external pin until the High byte is read. This instance prevents a
subsequent capture event from overwriting the High byte between the two Reads and
generating an invalid capture value. The capture value registers are Read Only.
A capture flag (ICA or ICB) in the TMRx_IIR register is set whenever a capture event
occurs. Setting the interrupt identification register bit TMRx_IER[IRQ_ICx_EN] enables
the capture event to generate a timer interrupt. The port pins must be configured as
alternate functions, see
GPIO Mode 7—Alternate Functions
on page 51.
Output Compare
The output compare function reverses the input capture function. Rather than store a timer
value when an external event occurs, OUTPUT COMPARE mode waits until the timer
reaches a specified value, then generates an external event. Although the same base timer
is used, up to four separate external pins are driven each with its own compare value.
To use OUTPUT COMPARE mode, the CPU must first configure the basic timer
parameters. Then it must load up to four 16-bit compare values into the four TMR3_OCx
register pairs. Next, it must load the TMR3_ OC_CTL2 register to specify the event that
occurs on comparison. You can select the following events: SET, CLEAR, and TOGGLE.
Finally, the CPU must enable OUTPUT COMPARE mode by asserting
TMR3_OC_CTL1[OC_EN].
The initial value for the OCx pins in OUTPUT COMPARE mode is 0 by default. It is
possible to initialize this value to 1 or force a value at a later time. Setting the
TMR3_OC_CTL2[OCx_MODE] value to 0 forces the OCx pin to the selected state
provided by the TMR3_OC_CTL1[OCx_INIT] bits. Regardless of any compare events,
the pin stays at the forced value until OCx_MODE is changed. After release, it retains the
forced value until modified by an OUTPUT COMPARE event.
PS027001-0707
Programmable Reload Timers