ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 134
ez80f91
Manufacturer Part Number
ez80f91
Description
Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
Manufacturer
ZiLOG Semiconductor
Datasheet
1.EZ80F91.pdf
(387 pages)
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PS027001-0707
TMR3_CTL Write
(Timer Enable)
System Clock
Clock Enable
Specialty Timer Modes
Timer Out
Timer Out
T3 Count
(internal)
(at pad)
Table 52. Example: PRT Timer Out Parameters
Break Point Halting
When the eZ80F91 device is running in DEBUG mode, encountering a break point causes
all CPU functions to halt. However, the timers keep running. This instance makes debug-
ging timer-related software much more difficult. Therefore, the control
register contains a BRK_STP bit. Setting this bit causes the count value to be held during
debug break points.
The features described above are common to all timers in the eZ80F91 device. In addition
to these common features, some of the timers have additional functionality.
Parameter
Timer Enable
Reload
Prescaler Divider = 4
CONTINUOUS Mode
Timer Reload Value
Figure 29. Example: PRT Timer Output Operation
0
4
3
Control Register(s)
TMR
TMR
TMR
TMR
{TMR
x
x
x
x
x
_CTL[TIM_EN]
_CTL[RLD]
_CTL[CLK_DIV]
_CTL[TIM_CONT]
_RR_H, TMRx_RR_L}
2
1
4
3
Programmable Reload Timers
Value
1
1
00b
1
0003h
Product Specification
2
eZ80F91 ASSP
1
126
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