ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 257
ez80f91
Manufacturer Part Number
ez80f91
Description
Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
Manufacturer
ZiLOG Semiconductor
Datasheet
1.EZ80F91.pdf
(387 pages)
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Table 137. ZDI Master Control Register (ZDI_MASTER_CTL = 11h in ZDI Register Write
Address Spaces)
PS027001-0707
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
7
ZDI_RESET
[6:0]
ZDI Master Control Register
The ZDI Master Control register provides control of the eZ80F91 device. It is capable of
forcing a RESET and waking up the eZ80F91 from the LOW-POWER modes (HALT or
SLEEP). See
Value
0
1
0000000 Reserved.
W
7
0
Table
Description
No action.
Initiate a RESET of the eZ80F91. This bit is automatically
cleared at the end of the RESET event.
W
137.
6
0
W
5
0
W
4
0
W
3
0
W
2
0
W
1
0
Product Specification
W
0
0
Zilog Debug Interface
eZ80F91 ASSP
249
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