ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 366

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Port Output
READ on Data Bus
General Purpose Input/Output Port Input Sample Timing
General Purpose I/O Port Output Timing
PHI
Input Value
GPIO Input
GPIO Data
Data Latch
GPIO Pin
Figure 74
pin is sampled on the rising edge of the system clock. The port value is then available to
the CPU on the second rising clock edge following the change of the port value.
Figure 75
PHI
T
1
illustrates timing of the GPIO input sampling. The input value on a GPIO port
and
Table 242
Figure 74. Port Input Sample Timing
Figure 75. GPIO Port Output Timing
T
CLK
Data Register
Port Value
Changes to 0
Into GPIO
0 Latched
on page 359 display timing information for GPIO port pins.
T
CLK
Product Specification
Electrical Characteristics
GPIO Data Register
Value 0 Read
by eZ80
T
eZ80F91 ASSP
2
358