ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 56

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 5. Clock Peripheral Power-Down Register 2
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit Position
7
PHI_OFF
6 VBO_OFF
[5:4]
3
TIMER3_OFF
2
TIMER2_OFF
1
TIMER1_OFF
0
TIMER0_OFF
Value Description
1
0
1
0
000
1
0
1
0
1
0
1
0
R/W
PHI Clock output is disabled (output is high-impedance).
PHI Clock output is enabled.
Voltage Brownout detection circuit is disabled. This reduces
DC current consumption in situations where VBO detection is
not necessary. Power-On Reset functionality is not affected by
this setting.
VBO detection circuit is enabled.
Reserved.
System clock to TIMER3 is powered down.
System clock to TIMER3 is powered up.
System clock to TIMER2 is powered down.
System clock to TIMER2 is powered up.
System clock to TIMER1 is powered down.
System clock to TIMER1 is powered up.
System clock to TIMER0 is powered down.
System clock to TIMER0 is powered up.
7
0
R/W
6
0
R
5
0
R
4
0
(CLK_PPD2 = 00DCh)
R/W
3
0
R/W
2
0
R/W
1
0
Product Specification
R/W
0
0
eZ80F91 ASSP
Low-Power Modes
48