ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 270

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 150. OCI Pins
PS027001-0707
Symbol
TCK
TRSTn
TMS
TDI
OCI Activation
OCI Interface
Name
Clock
TAP Reset
Test Mode Select
Data In
OCI features clock initialization circuitry so that external debug hardware is detected dur-
ing power-up. The external debugger must drive the OCI clock pin (TCK) Low at least
two system clock cycles prior to the end of the RESET to activate the OCI block. If TCK
is High at the end of the RESET, the OCI block shuts down so that it does not draw power
in normal product operation. When the OCI is shut down, ZDI is enabled directly and is
accessed via the clock (TCK) and data (TDI) pins. For more information on ZDI, see
Debug Interface
There are six dedicated pins on the eZ80F91 for the OCI interface. Four pins—TCK,
TMS, TDI, and TDO—are required for IEEE Standard 1149.1-compliant JTAG ports. A
fifth pin, TRSTn, is optional for IEEE 1149.1 and utilized by the eZ80F91 device. The
TRIGOUT pin provides additional testability features. These six OCI pins are described in
Table
150.
on page 235.
Type
Input
Input
Input
Input
(OCI enabled)
I/O
(OCI disabled)
Description
Asynchronous to the primary eZ80F91 system clock.
The TCK period must be at least twice the system
clock period. During RESET, this pin is sampled to
select either OCI or ZDI DEBUG modes. If Low
during RESET, the OCI is enabled. If High during
RESET, the OCI is powered down and ZDI DEBUG
mode is enabled. When ZDI DEBUG mode is active,
this pin is the ZDI clock. On-chip pull-up ensures a
default value of 1 (High).
Active Low asynchronous reset for the Test Access
Port state register. On-chip pull-up ensures a default
value of 1 (High).
This serial test mode input controls JTAG mode
selection. On-chip pull-up ensures a default value of
1 (High). The TMS signal is sampled on the rising
edge of the TCK signal.
Serial test data input. This pin is input-only when the
OCI is enabled. The input data is sampled on the
rising edge of the TCK signal.
When the OCI is disabled, this pin functions as the
ZDA (ZDI Data) I/O pin. NORMAL mode, following
RESET, configures TDI as an input.
Product Specification
On-Chip Instrumentation
eZ80F91 ASSP
Zilog
262