ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 309

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
EMAC Operation in HALT Modes
EMAC Registers
transfer capabilities at certain system operating frequencies, you must first understand the
internal data bus bandwidth that is required under ideal conditions.
For 10 BaseT Ethernet connectivity, the data rate is 10 Mbps, which equates to 1.25 Mbps.
If the eZ80F91 ASSP is operating in FULL-DUPLEX mode over 10BaseT, the data rate for
RX data and TX data is 1.25 Mbps. Because raw data transfers at this rate consume a cer-
tain amount of CPU bandwidth, the CPU must support traffic from both directions as well
as operate at a minimum clock frequency of (1.25 + 1.25) * 2 = 5 MHz while transferring
Ethernet packets to and from the physical layer.
Similarly, for 100 BaseT Ethernet, the data rate is 100 Mbps, which equates to 12.5 Mbps.
If the eZ80F91 ASSP is operating in FULL-DUPLEX mode over 100 BaseT, the data rate
for RX data and TX data is 12.5 Mbps. Because raw data transfers at this rate consume a
certain amount of CPU bandwidth, the CPU must support traffic from both directions as
well as operate at a minimum clock frequency of (12.5 + 12.5) x 2 = 50 MHz while trans-
ferring Ethernet packets to and from the physical layer. Consequently, 50 MHz is the min-
imum system clock speed that the eZ80 CPU requires to sustain EMAC data transfers
while not including any software overhead or additional eZ80 tasks.
The FIFO functionality of the EMAC operates at any frequency as long as the user appli-
cation avoids overrun and underrun errors via higher-level flow control. Actual applica-
tion requirements will dictate Ethernet modes of operation (FULL-DUPLEX, HALF-
DUPLEX, etc.). Because each user and application is different, it becomes your responsi-
bility to control the data flow with these parameters. Under ideal conditions, the system
clock will operate somewhere between 5 MHz and 50 MHz to handle the EMAC data
rates.
When the CPU is in HALT mode, the eZ80F91 device’s EMAC block cannot be disabled
as other peripherals. Upon receipt of an Ethernet packet, a maskable Receive interrupt is
generated by the EMAC block, just as it would be in a non-halt mode. Accordingly, the
processor wakes up and continues with the user-defined application.
After a system reset, all EMAC registers are set to their default values. Any Writes to
unused registers or register bits are ignored and reads return a value of 0. For compatibil-
ity with future revisions, unused bits within a register must always be written with a value
of 0. Read/Write attributes, reset conditions, and bit descriptions of all of the EMAC reg-
isters are provided in this section.
Ethernet Media Access Controller
Product Specification
eZ80F91 ASSP
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