ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 137

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Timer Port Pin Allocation
Asserting TMR3_OC_CTL1[MAST_MODE] selects MASTER MODE for all OUTPUT
COMPARE events and sets output 0 as the master. As a result, outputs 1, 2, and 3 are
caused to disregard output-specific configuration and comparison values and instead
mimic the current settings for output 0.
The OCx bits in the TMR3_IIR register are set whenever the corresponding timer com-
pares occur. TMR3_IER[IRQ_OCx_EN] allows the compare event to generate a timer
interrupt.
The eZ80F91 device timers interface to the outside world via Ports A and B. These
ports are also used for GPIO as well as other assorted functions.
lists the timer pins and their respective functions.
Table 53. GPIO Mode Selection Using Timer Pins
Port
A
B
GPIO Port
PB0
PB1
PB4
PB5
Bits
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
GPIO Port
Mode
7
7
7
7
7
7
7
7
7
7
7
7
MPWM_EN = 0
PAIR_EN = 0
PWM_CTL1
PWM_CTL1
TOUT0
TOUT2
OC0
OC1
OC2
OC3
EC1
Timer Function
IC0/EC0
IC1
IC2
IC3
Programmable Reload Timers
MPWM_EN = 1
PAIR_EN = 1
Product Specification
Table 53
PWM_CTL1
PWM_CTL1
PWM0
PWM1
PWM2
PWM3
PWM0
PWM1
PWM2
PWM3
eZ80F91 ASSP
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