ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 77

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Caution:
WAIT Input Signal
Similar to the programmable wait states, an external peripheral drives the WAIT input pin
to force the CPU to provide additional clock cycles to complete its Read or Write opera-
tion. Driving the WAIT pin Low stalls the CPU. The CPU resumes operation on the first
rising edge of the internal system clock following deassertion of the WAIT pin.
An example of wait state operation is illustrated in
the chip select is configured to provide a single wait state. The external peripheral
accessed drives the WAIT pin Low to request assertion of an additional wait state. If the
WAIT pin is asserted for additional system clock cycles, wait states are added until the
WAIT pin is deasserted (active High).
Wait
Pin
If the WAIT pin is to be driven by an external device, the corresponding chip select for
the device must be programmed to provide at least one wait state. Due to input sampling
of the WAIT input pin (see
the external peripheral sufficient time to assert the WAIT pin. It is recommended that
the corresponding chip select for the external device be programmed to provide the
maximum number of wait states (seven).
System Clock
D
Figure 8. Wait Input Sampling Block Diagram
Q
Figure
eZ80
CPU
8), one programmable wait state is required to allow
Figure 9
on page 70. In this example,
Chip Selects and Wait States
Product Specification
eZ80F91 ASSP
69