ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 99

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Figure 20. Memory Interface Bus Operation During CPU Bus Cycles, Normal Operation
Figure 21. Memory Interface Bus Operation During Bus Acknowledge Cycles
During bus acknowledge cycles, the Memory and I/O chip select logic is controlled by the
external address bus and external IORQ and MREQ signals.
External
External
Master
Master
MREQ
MREQ
IORQ
IORQ
Chip Select
Chip Select
Wait State
Wait State
Generator
Generator
eZ80F91
eZ80F91
ADDRESS
ADDRESS
DATA
DATA
WAIT
WAIT
WR
WR
RD
RD
CS0
CS1
CS2
CS3
CS0
CS1
CS2
CS3
Chip Selects and Wait States
Peripheral
Peripheral
Product Specification
External
External
eZ80F91 ASSP
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