ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 155

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
T3 Count
PWM0
PWM0
PWM1
PWM1
System Clock
Clock Enable
T3 Count
0
The inverted PWM outputs PWM0, PWM1, PWM2, and PWM3 are globally enabled by
setting TMR3_PWM_CTL1[PAIR_EN] to 1. The individual PWM generators must be
enabled for the associated inverted PWM signals to be output.
For each of the 4 PWM generators, there is a 16-bit rising edge value
{TMR3_PWMxR_H[PWMxR_H], TMR3_PWMxR_L[PWMxR_L]} and a 16-bit falling
edge value {TMR3_PWMxF_H[PWMxF_H], TMR3_PWMxF_L[PWMxF_L]} for a total
of 16 registers. The rising-edge byte pairs define the timer count at which the PWMx
output transitions from Low to High. Conversely, the falling-edge byte pairs define the
timer count at which the PWMx output transitions from High to Low. On reset, all enabled
PWM outputs begin Low and all PWMx outputs begin High. When the PWMx output is
Low, the logic is looking for a match between the timer count and the rising edge value,
and vice versa. Therefore, in a case in which the rising edge value is the same as the falling
edge value, the PWM output frequency is one-half the rate at which the counter passes
through its entire count cycle (from reload value down to
Figure
of the timing, respectively. Associated control values are listed in
Figure 32. Multi-PWM Operation—Expanded View of Timing
C B A 9 8 7 6 5 4 3 2 1 C B A 9 8 7 6 5 4 3 2 1 C B A
31and
Figure 32
A
Figure 31. Multi-PWM Operation
demonstrate a simple Multi-PWM output and an expanded view
9
8
7
0000h
6
9 8 7 6 5 4 3 2 1
Programmable Reload Timers
Product Specification
).
Table
71.
5
eZ80F91 ASSP
C B A
4
147