ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 194

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 99. UART Interrupt Identification Registers
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
[7]
FSTS
[6:4]
[3:1]
INSTS
0
INTBIT
UART Interrupt Identification Register
The Read Only UARTx_IIR register allows you to check whether the FIFO is enabled and
the status of interrupts. These registers share the same I/O addresses as the UARTx_FCTL
registers. See
Table 100. UART Interrupt Status Codes
Value
0
1
000
000–
110
0
1
INSTS
Value
011
010
110
101
001
000
Description
FIFO is disabled.
FIFO is enabled.
Reserved
Interrupt Status Code
The code indicated in these three bits is valid only if INTBIT is
1. If two internal interrupt sources are active and their
respective enable bits are High, only the higher priority
interrupt is seen by the application. The lower-priority interrupt
code is indicated only after the higher-priority interrupt is
serviced.
There is an active interrupt source within the UART.
There is not an active interrupt source within the UART.
Priority
Highest
Second
Third
Fourth
Fifth
Lowest
R
7
0
Table 99
R
6
0
Table 100
and
Interrupt Type
Receiver Line Status
Receive Data Ready or Trigger Level
Character Time-out
Transmission Complete
Transmit Buffer Empty
Modem Status
Table
R
5
0
lists the interrupt status codes.
100.
R
4
0
(UART0_IIR = 00C2h, UART1_IIR = 00D2h)
R
3
0
Universal Asynchronous Receiver/Transmitter
R
2
0
R
1
0
Product Specification
R
0
1
eZ80F91 ASSP
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