ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 218

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 114. SPI Control Register
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit
Position
7
IRQ_EN
6
5
SPI_EN
4
MASTER_EN
3
CPOL
2
CPHA
[1:0]
SPI Control Register
This register is used to control and setup the serial peripheral interface. The SPI must be
disabled prior to making any changes to CPHA or CPOL. See
Value Description
0
1
0
0
1
0
1
0
1
0
1
00
R/W
SPI system interrupt is disabled.
SPI system interrupt is enabled.
Reserved.
SPI is disabled.
SPI is enabled.
When enabled, the SPI operates as a slave.
When enabled, the SPI operates as a master.
Master SCK pin idles in a Low (0) state.
Master SCK pin idles in a High (1) state.
SS must go High after transfer of every byte of data.
SS remains Low to transfer any number of data bytes.
Reserved.
7
0
R
6
0
(SPI_CTL = 00BAh)
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
1
R
1
0
Table
Product Specification
Serial Peripheral Interface
114.
R
0
0
eZ80F91 ASSP
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