ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 159

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Note:
System Clock
TMR3_Count
Clock Enable
PWM0
PWM0
setting of 0000b represents a delay of 0 system clock periods and a setting of 1111b rep-
resents a delay of 15 system clock periods. The PWM delay feature is illustrated in
Figure 34
The PWM nonoverlapping delay time must always be defined to be less than the delay
between the rising and falling edges (and the delay between the falling and rising edges) of
all Multi-PWM outputs. In other words, a rising (falling) edge cannot be delayed beyond
the time at which it is subsequently scheduled to fall (rise).
Table 72. PWM Nonoverlapping Output Addressing
Parameter
Timer clock is SCLK ÷ 4
Timer reload value
PWM0 rising edge
PWM0 falling edge
Prescaler divider = 4
PWM nonoverlapping delay = 3
PWM enable
PWM0 enable
Multi-PWM enable
A
Figure 34. PWM Nonoverlapping Output Delay
with associated addressing listed in
9
8
7
Control Register(s)
{TMR3_RR_H, TMR3_RR_L}
{TMR3_PWM0R_H, TMR3_PWM0R_L}
{TMR3_PWM0F_H, TMR3_PWM0F_L}
TMR3_PWM_CTL2[PWM_DLY]
TMR3_PWM_CTL1[PAIR_EN]
TMR3_PWM_CTL1[PWM0_EN]
TMR3_PWM_CTL1[MPWN_EN]
TMR3_CTL[CLK_DIV]
TMR3_CTL[CLK_DIV]
3 x SCLK
6
Table
5
72.
4
Programmable Reload Timers
3
Product Specification
3 x SCLK
2
eZ80F91 ASSP
0008h
0004h
1
1
1
Value
00b
000Ch
00b
0011b
1
C
151