ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 238

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 128. I
Table 129. I
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
[7:3]
STAT
[2:0]
Code
00h
08h
10h
18h
20h
28h
30h
38h
Status
Bus error.
START condition transmitted.
Repeated START condition transmitted.
Address and Write bit transmitted, ACK received.
Address and Write bit transmitted, ACK not received.
Data byte transmitted in MASTER mode, ACK received.
Data byte transmitted in MASTER mode, ACK not received.
Arbitration lost in address or data byte.
2
2
C Status Registers
C Status Codes
I
The I
most-significant bits; the three least-significant bits are always 0. The Read Only
I2C_SR registers share the same I/O addresses as the Write Only I2C_CCR registers.
See
There are 29 possible status codes, as listed in
contains the status code
generated, and the IFLG bit in the I
correspond to a defined state of the I
When each of these states is entered, the corresponding status code appears in this register
and the IFLG bit in the I
tus code returns to
2
C Status Register
Value
00000–
11111
000
Table
2
C_SR register is a Read Only register that contains a 5-bit status code in the five
128.
R
7
1
Description
5-bit I
Reserved.
F8h
R
6
1
2
(I2C_SR = 00CCh)
C status code.
.
F8h
2
C_CTL register is set to 1. When the IFLG bit is cleared, the sta-
R
5
1
, no relevant status information is available, no interrupt is
2
R
4
1
C_CTL register is not set. All other status codes
2
C.
R
3
1
Table
R
2
0
129. When the I
R
1
0
Product Specification
R
2
0
0
I
C_SR register
2
C Serial I/O Interface
eZ80F91 ASSP
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