ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 237

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 127. I
PS027001-0707
Bit
Reset
CPU Access
Note: R/W = Read/Write; R = Read Only.
Bit
Position
7
IEN
6
ENAB
5
STA
4
STP
3
IFLG
2
AAK
[1:0]
2
C Control Register
Value Description
0
1
0
1
0
1
0
1
0
1
0
1
00
R/W
I
I
The I
The I
Master mode START condition is sent.
Master mode start-transmit START condition on the bus.
Master mode STOP condition is sent.
Master mode stop-transmit STOP condition on the bus.
I
I
Not Acknowledge.
Acknowledge.
Reserved.
7
0
2
2
2
2
C interrupt is disabled.
C interrupt is enabled.
C interrupt flag is not set.
C interrupt flag is set.
2
2
C bus (SCL/SDA) is disabled and all inputs are ignored.
C bus (SCL/SDA) is enabled.
R/W
6
0
(I2C_CTL = 00CBh)
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R
1
0
Product Specification
R
0
0
I
2
C Serial I/O Interface
eZ80F91 ASSP
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