ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 209

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 110. Infrared Encoder/Decoder Control Registers
PS027001-0707
Bit
Reset
CPU Access
Note:
Bit
Position
[7:4]
MIN_PULSE
3
2
LOOP_BACK
1
IR_RxEN
0
IR_EN
R = Read only; R/W = Read/Write.
Infrared Encoder/Decoder Register
After a RESET, the Infrared Encoder/Decoder Register is set to its default value. Any
Writes to unused register bits are ignored and reads return a value of 0. The IR_CTL regis-
ter is described in
Value
0000
1h-Fh
0
0
1
0
1
0
1
R/W
Description
Minimum receive pulse width control. When this field is equal to
0x0, the IrDA decoder uses edge detection to accept arbitrarily
narrow (that is, short) input pulses.
When not equal to 0x0, this field forms the most-significant four
bits of the 6-bit down-counter used to determine if an input
pulse will be ignored because it is too narrow. The lower two
counter bits are hard-coded to load with 0x3, resulting in a total
down-count equal to ((IR_CTL[4:0]MIN_PULSE * 4) + 3). To be
accepted, input pulses must have a width greater than or equal
to the down-count value times the system clock period.
Reserved.
Internal LOOP BACK mode is disabled.
Internal LOOP BACK mode is enabled.
IR_TxD output is inverted and connected to IR_RxD input for
internal loop back testing.
IR_RxD data is ignored.
IR_RxD data is passed to UART0
Endec is disabled.
Endec is enabled.
7
0
Table
R/W
6
0
110.
R/W
5
0
R/W
4
0
R
3
0
R
x
D
.
(IR_CTL = 00BFh)
R/W
2
0
R/W
1
0
Product Specification
Infrared Encoder/Decoder
R/W
0
0
eZ80F91 ASSP
201