AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 100

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

The PCI Device ID register is located at offset 02h in
the PCI Configuration Space. It is read only.
PCI Command Register
Offset 04h
The PCI Command register is a 16-bit register used to
control the gross functionality of the Am79C978A con-
troller. It controls the Am79C978A controller’s ability to
generate and respond to PCI bus cycles. To logically
disconnect the Am79C978A device from all PCI bus
cycles except configuration cycles, a value of 0 should
be written to this register.
The PCI Command register is located at offset 04h in
the PCI Configuration Space. It is read and written by
the host.
Bit
15-10
9
8
7
6
100
Name
RES
FBTBEN
SERREN
RES
PERREN
Description
Reserved locations. Read as ze-
ros; write operations have no
effect.
Fast Back-to-Back Enable. Read
as zero; write operations have no
effect. The Am79C978A control-
ler
Back-to-Back cycles.
SERR Enable. Controls the as-
sertion of the SERR pin. SERR is
disabled
cleared. SERR will be asserted
on detection of an address parity
error and if both SERREN and
PERREN (bit 6 of this register)
are set.
SERREN
H_RESET and is not effected by
S_RESET or by setting the STOP
bit.
Reserved location. Read as ze-
ros; write operations have no
effect.
Parity Error Response Enable.
Enables the parity error response
functions. When PERREN is 0
and the Am79C978A controller
detects a parity error, it only sets
the Detected Parity Error bit in
the PCI Status register. When
PERREN is 1, the Am79C978A
controller asserts PERR on the
detection of a data parity error. It
also sets the DATAPERR bit (PCI
Status register, bit 8), when the
will
not
when
is
generate
cleared
SERREN
Fast
Am79C978A
by
is
5
4
3
2
1
VGASNOOP
MWIEN
SCYCEN
BMEN
MEMEN
data parity error occurred during
a master cycle. PERREN also
enables reporting address parity
errors through the SERR pin and
the SERR bit in the PCI Status
register.
H_RESET and is not affected by
S_RESET or by setting the STOP
bit.
ro; write operations have no
effect.
cle Enable. Read as zero; write
operations have no effect. The
Am79C978A controller only gen-
erates Memory Write cycles.
zero; write operations have no ef-
fect. The Am79C978A controller
ignores all Special Cycle opera-
tions.
BMEN enables the Am79C978A
controller to become a bus mas-
ter on the PCI bus. The host must
set BMEN before setting the INIT
or STRT bit in CSR0 of the
Am79C978A controller.
and is not effected by S_RESET
or by setting the STOP bit.
The Am79C978A controller will
ignore all memory accesses
when MEMEN is cleared. The
host must set MEMEN before the
first memory access to the
device.
host must program the PCI Mem-
ory Mapped I/O Base Address
register with a valid memory ad-
dress before setting MEMEN.
For accesses to the Expansion
ROM, the host must program the
PCI
Address register at offset 30h
with a valid memory address
PERREN
VGA Palette Snoop. Read as ze-
Memory Write and Invalidate Cy-
Special Cycle Enable. Read as
Bus
BMEN is cleared by H_RESET
Memory Space Access Enable.
For memory mapped I/O, the
Master
Expansion
is
Enable.
cleared
ROM
Setting
Base
by