AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 168

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

11
10-8
7
168
110-111
APDW
000
001
010
011
100
101
FMDC
00
01
10
11
APEP
APDW
DANAS
Continuous (26 s @ 2.5 MHz)
Every 128 MDC cycles (103 s @ 2.5 MHz)
Every 256 MDC cycles (206 s @ 2.5 MHz)
Every 512 MDC cycles (410 s @ 2.5 MHz)
Every 1024 MDC cycles (819 s @ 2.5 MHz)
Every 2048 MDC cycles (1640 s @ 2.5 MHz)
Reserved
Table 45. FMDC Values
Table 46. APDW Values
Fast Management Data Clock
compliant to IEEE 802.3u stan-
dards. See Table 45.
This bit is always read/write ac-
cessible. FMDC is set to 0 during
H_RESET, and is unaffected by
S_RESET and the STOP bit
Auto-Poll PHY. When APEP is
set to 1 the Am79C978A control-
ler will poll the status register in
the PHY. This feature allows the
software driver or upper layers to
see any changes in the status of
the PHY. An interrupt when en-
abled is generated when the con-
tents of the new status is different
from the previous status.
This bit is always read/write ac-
cessible. APEP is set to 0 during
H_RESET and is unaffected by
S_RESET and the STOP bit.
Auto-Poll Dwell Time. APDW de-
termines the dwell time between
PHY
accesses
turned on. See Table 46.
This bit is always read/write ac-
cessible. APDW is set to 100h af-
ter H_RESET and is unaffected
by S_RESET and the STOP bit.
Disable
Auto Setup. When DANAS is
set, the Am79C978A control-
ler
Auto-Poll
after
2.5 MHz max
10 MHz max
5 MHz max
Reserved
Management
Dwell Time
when
a
Auto-Negotiation
H_RESET
Auto-Poll
Frame
Am79C978A
or
is
6
5
4
XPHYRST
XPHYANE
XPHYFD
S_RESET will remain dor-
mant and not automatically
startup the Auto-Negotiation
section or the enhanced auto-
matic port selection section.
Instead,
controller will wait for the
software driver to setup the
Auto-Negotiation portions of
the device. The PHY Address
and
BCR33 and BCR34 is still val-
id. The Am79C978A control-
ler
management frames unless
Auto-Poll is enabled.
This bit is always read/write ac-
cessible. DANAS is set to 0 by
H_RESET and is unaffected by
S_RESET and the STOP bit.
PHY Reset. When XPHYRST is
set, the Am79C978A controller
after an H_RESET or S_RESET
will issue management frames
that will reset the PHY. This bit is
needed when there is no way to
guarantee the state of the exter-
nal PHY. This bit must be repro-
grammed after every H_RESET.
This bit is always read/write ac-
cessible. XPHYRST is set to 0 by
H_RESET and is unaffected by
S_RESET and the STOP bit.
XPHYRST is only valid when the
internal Network Port Manager is
scanning for a network port.
PHY Auto-Negotiation Enable.
This bit will force the PHY into en-
abling Auto-Negotiation. When
set to 0 the Am79C978A control-
ler will send a management frame
disabling Auto-Negotiation.
This bit is always read/write ac-
cessible. XPHYANE is set to 0 by
H_RESET and is unaffected by
S_RESET and the STOP bit.
XPHYANE is only valid when the
internal Network Port Manager is
scanning for a network port.
PHY Full Duplex. When set, this
bit will force the PHY into full du-
plex when Auto-Negotiation is
not enabled.
will
Data
not
the
programming
generate
Am79C978A
any
in