AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 37

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AM79C978A

Manufacturer Part Number
AM79C978A
Description
Single-Chip 1/10 Mbps PCI Home Networking Controller
Manufacturer
AMD [Advanced Micro Devices]
Datasheet

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Figure 9. Disconnect of Slave Burst Transfer - No
Figure 8.
DEVSEL
FRAME
DEVSEL
FRAME
STOP
TRDY
TRDY
STOP
C/BE
IRDY
C/BE
IRDY
CLK
PAR
PAR
CLK
AD
AD
Disconnect of Slave Cycle When Busy
1
1
Host Wait States
ADDR
CMD
1st DATA
2
BE
2
PAR
PAR
3
DATA
3
BE
DATA
BE
4
PAR
4
PAR
5
22399A-11
22399A-12
5
Am79C978A
Parity Error Response
When the Am79C978A controller is not the current bus
master, it samples the AD[31:0], C/BE[3:0], and the
PAR lines during the address phase of any PCI com-
mand for a parity error. When it detects an address par-
ity error, the Am79C978A controller sets PERR (PCI
Status register, bit 15) to 1. When reporting of that error
is enabled by setting SERREN (PCI Command regis-
ter, bit 8) and PERREN (PCI Command register, bit 6)
to 1, the Am79C978A controller also drives the SERR
signal low for one clock cycle and sets SERR (PCI Sta-
tus register, bit 14) to 1. The assertion of SERR follows
t h e a d d r e s s p h a s e by two c l o ck c y c l e s . T h e
Am79C978A controller will not assert DEVSEL for a
PCI transaction that has an address parity error when
PERREN and SERREN are set to 1. See Figure 11.
Figure 10. Disconnect of Slave Burst Transfer -
DEVSEL
FRAME
STOP
TRDY
C/BE
IRDY
CLK
PAR
AD
1
Host Inserts Wait States
1st DATA
2
BE
PAR
3
4
DATA
BE
5
PAR
22399A-13
6
37

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