AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 181
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AM79C978A
Manufacturer Part Number
AM79C978A
Description
Single-Chip 1/10 Mbps PCI Home Networking Controller
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C978A.pdf
(256 pages)
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TBR4: 10BASE-T Auto-Negotiation Advertisement
Register (Register 4)
This register contains the advertised ability of the
Am79C978A home networking device. The purpose of
Bit(s)
12:11
4:0
15
14
13
10
9
8
7
6
5
Half-Duplex –
Half-Duplex –
Selector Field
Remote Fault
Full-Duplex –
100BASE-TX
100BASE-TX
Full-Duplex –
Next Page
10BASE-T
10BASE-T
Table 52. TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register 4)
Reserved
Reserved
Reserved
PAUSE
Name
When set, the device wishes to engage in next page exchange. If
clear, the device does not wish to engage in next page exchange.
When set, a remote fault bit is inserted into the base link code
word during the Auto Negotiation process. When cleared, the
base link code work will have the bit position for remote fault as
cleared.
This bit should be set if the PAUSE capability is to be advertised.
This bit advertises Full-Duplex capability. When set, Full-Duplex
capability is advertised. When cleared, Full-Duplex capability is
not advertised.
This bit advertises Half-Duplex capability for the Auto-negotiation
process. Setting this bit advertises half-duplex capability. Clearing
this bit does not advertise half-duplex capability.
This bit advertises Full-Duplex capability. When set, Full-Duplex
capability is advertised. When cleared, Full-Duplex capability is
not advertised.
This bit advertises Half-Duplex capability for the Auto-negotiation
process. Setting this bit advertises Half-Duplex capability.
Clearing this bit does not advertise Half-Duplex capability.
The Am79C978A home networking device is an 802.3 compliant
device
Am79C978A
Description
this register is to advertise the technology ability to the
link partner device. See Table 52.
When this regi ster is modified, Restar t Auto-
Negotiation (Register 0, bit 9) must be enabled to
guarantee the change is implemented.
Read/
Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
H/W or Soft
Reset
0x01
0
0
0
0
0
0
0
0
1
1
181
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