AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 139

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

CSR92: Ring Length Conversion
Bit
31-16 RES
15-0
CSR100: Bus Timeout
Bit
31-16 RES
15-0
RCON
MERRTO
Name
Name
Ring Length Conversion Regis-
This register contains the value of
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. PARTIDU is
read only. Write operations are
ignored.
Reserved locations. Written as
zeros and read as undefined.
ter. This register performs a ring
length conversion from an encod-
ed value as found in the initializa-
tion block to a two’s complement
value used for internal counting.
By writing bits 15-12 with an en-
coded ring length, a two’s com-
plemented value is read. The
RCON register is undefined until
written.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Reserved locations. Written as
zeros and read as undefined.
the longest allowable bus latency
(interval between assertion of
REQ and assertion of GNT) that a
system
Am79C978A controller master
transfer. If this value of bus laten-
cy is exceeded, then a MERR will
be indicated in CSR0, bit 11, and
an interrupt may be generated,
depending upon the setting of the
MERRM bit (CSR3, bit 11) and
the IENA bit (CSR0, bit 6).
The value in this register is inter-
preted as the unsigned number of
bus clock periods divided by two,
(i.e., the value in this register is
given in 0.1 ms increments). For
example, the value 0600h (1536
decimal) will cause a MERR to be
Description
Description
may
insert
into
Am79C978A
an
CSR112: Missed Frame Count
Bit
31-16 RES
15-0
CSR114: Receive Collision count
Bit
31-16 RES
15-0
MFC
RCC
Name
Name
Reserved locations. Written as
Reserved locations. Written as
Receive Collision Count. Indi-
indicated after 153.6 ms of bus la-
tency. A value of 0 will allow an in-
finitely long bus latency, i.e., bus
timeout error will never occur.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. This regis-
ter is set to 0600h by H_RESET
or S_RESET and is unaffected by
STOP.
zeros and read as undefined.
Missed Frame Count. Indicates
the number of missed frames.
MFC will roll over to a count of 0
from the value 65535. The MFCO
bit of CSR4 (bit 8) will be set each
time that this occurs.
Read accessible always. MFC is
read only, write operations are ig-
nored.
H_RESET, or S_RESET or by
setting the STOP bit.CSR114:
Receive Collision Count
zeros and read as undefined.
cates the total number of colli-
sions
receiver since the last reset of the
counter.
RCC will roll over to a count of 0
from the value 65535. The
RCVCCO bit of CSR4 (bit 5) will
be set each time that this occurs.
These bits are read accessible al-
ways. RCC is read only, write op-
erations are ignored. RCC is
cleared
S_RESET, or by setting the
STOP bit.
Description
Description
encountered
MFC
by
is
H_RESET
cleared
by
139
the
by
or