AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 40

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

Am79C978A controller supports zero wait state read
cycles. It asserts IRDY immediately after the address
phase and at the same time starts sampling DEVSEL.
Figure 14 shows two non-burst read transactions. The
first transaction has zero wait states. In the second
transaction, the target extends the cycle by asserting
TRDY one clock later.
Basic Burst Read Transfer
The Am79C978A controller supports burst mode for
all bus master read operations. The burst mode
must be enabled by setting BREADE (BCR18, bit
6). To allow burst transfers in descriptor read oper-
ations, the Am79C978A controller must also be pro-
grammed to use SWSTYLE 3 (BCR20, bits 7-0). All
burst read accesses to the initialization block and
descriptor ring are of the PCI command type Mem-
ory Read (type 6). Burst read accesses to the trans-
mit buffer typically are longer than two data phases.
When MEMCMD (BCR18, bit 9) is cleared to 0, all
burst read accesses to the transmit buffer are of the
PCI command type Memory Read Line (type 14).
When MEMCMD (BCR18, bit 9) is set to 1, all burst
read accesses to the transmit buffer are of the PCI
command type Memory Read Multiple (type 12).
40
DEVSEL
FRAME
TRDY
C/BE
IRDY
REQ
GNT
CLK
PAR
AD
1
DEVSEL is sampled
2
Figure 14. Non-Burst Read Transfer
ADDR
0110
3
PAR
4
0000
Am79C978A
DATA
5
PAR
AD[1:0] will both be 0 during the address phase in-
dicating a linear burst order. Note that during a
burst read operation, all byte lanes will always be
active. The Am79C978A controller will internally
discard unneeded bytes.
The Am79C978A controller will always perform only a
single burst read transaction per bus mastership pe-
riod, where transaction is defined as one address
ph as e an d o ne or mul ti pl e da ta p ha s es. Th e
Am79C978A controller supports zero wait state read
cycles. It asserts IRDY immediately after the address
phase and at the same time starts sampling DEVSEL.
FRAME is deasserted when the next to last data phase
is completed.
Figure 15 shows a typical burst read access. The
Am79C978A controller arbitrates for the bus, is
granted access, reads three 32-bit words (DWord)
from the system memory, and then releases the bus.
In the example, the memory system extends the data
phase of each access by one wait state. The exam-
ple assumes that EXTREQ (BCR18, bit 8) is cleared
to 0, therefore, REQ is deasserted in the same cycle
as FRAME is asserted.
6
ADDR
0110
7
PAR
8
0000
9
DATA
10
PAR
11
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