AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 131

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

CSR49: Receive Polling Interval
Bit
31-16 RES
15-0
RXPOLLINT Receive Polling Interval. This reg-
Name
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Reserved locations. Written as
zeros and read as undefined.
ister contains the time that the
Am79C978A controller will wait
between successive polling oper-
ations. The RXPOLLINT value is
expressed as the two’s comple-
ment of the desired interval, where
each bit of RXPOLLINT repre-
sents approximately one clock
time period. RXPOLLINT[3:0] are
ignored. (RXPOLLINT[16] is im-
plied to be a 1, so RXPOLLINT[15]
is significant and does not repre-
sent the sign of the two’s comple-
ment RXPOLLINT value.)
The default value of this register is
0000h. This corresponds to a poll-
ing interval of 65,536 clock peri-
ods (1.966 ms when CLK = 33
MHz). The RXPOLLINT value of
0000h is created during the micro-
code initialization routine and,
therefore, might not be seen when
reading CSR49 after H_RESET or
S_RESET.
If the user desires to program a
value for RXPOLLINT other than
the default, then the correct pro-
cedure is to first set INIT only in
CSR0. Then, when the initializa-
tion sequence is complete, the
user must set STOP (CSR0, bit
2). Then the user may write to
CSR49 and set STRT in CSR0.
In this way, the default value of
0000h in CSR47 will be overwrit-
ten with the desired user value.
If the user does not use the stan-
dard initialization procedure (stan-
dard implies use of an initialization
block in memory and setting the
INIT bit of CSR0), but instead
chooses to write directly to each of
Description
Am79C978A
CSR58: Software Style
This register is an alias of the location BCR20. Access-
es to and from this register are equivalent to accesses
to BCR20.
Bit
31-11 RES
10
9
8
APERREN
RES
SSIZE32
Name
Reserved locations. Written as
Software Size 32 bits. When set,
the registers that are involved in
the INIT operation, it is imperative
that the user also writes all zeros
to CSR49 as part of the alternative
initialization sequence.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
Advanced Parity Error Handling
Enable. When APERREN is set
to 1, the BPE bits (RMD1 and
TMD1, bit 23) start having a
meaning. BPE will be set in the
descriptor associated with the
buffer that was accessed when a
data parity error occurred. Note
that since the advanced parity
error handling uses an additional
bit in the descriptor, SWSTYLE
(bits 7-0 of this register) must be
set to 2 or 3 to program the
Am79C978A controller to use
32-bit software structures.
APERREN does not affect the re-
porting of address parity errors or
data parity errors that occur when
the Am79C978A controller is the
target of the transfer.
Read anytime, write accessible
only when either the STOP or the
SPND bit is set. APERREN is
cleared by H_RESET and is not
affected by S_RESET or STOP.
Reserved location. Written as
zero and read as undefined.
this
Am79C978A controller utilizes
32-bit software structures for the
initialization block and the trans-
mit and receive descriptor en-
Description
bit
indicates
that
131
the