AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 112

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

CSR1: Initialization Block Address 0
Bit
31-16
15-0
CSR2: Initialization Block Address 1
Bit
31-16
15-8
112
Name
RES
IADR[15:0] Lower 16 bits of the address of
Name
RES
IADR[31:24] If SSIZE32 is set (BCR20, bit 8),
This bit is always read/write ac-
cessible. INIT is set by writing a 1.
Writing a 0 has no effect. INIT is
cleared
S_RESET, or by setting the
STOP bit.
This register is aliased with
CSR16.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or by setting the
STOP bit.
However, if SSIZE32 is reset
(BCR20,
IADR[31:24] bits will be used to
generate the upper 8 bits of all
bus mastering addresses, as re-
quired for a 32-bit address bus.
Note that the 16-bit software
structures
SSIZE32 = 0 setting will yield
only 24 bits of address for the
Am79C978A bus master ac-
cesses, while the 32-bit hard-
ware for which the Am79C978A
controller initialization will be per-
formed first. INIT is not cleared
when the initialization sequence
has completed.
Description
Reserved locations. Written as
zeros and read as undefined.
the Initialization Block. Bit loca-
tions 1 and 0 must both be 0 to
align the initialization block to a
DWord boundary.
Description
Reserved locations. Written as
zeros and read as undefined.
then the IADR[31:24] bits will be
used strictly as the upper 8 bits of
the initialization block address.
bit
specified
by
8),
H_RESET,
then
by
Am79C978A
the
the
7-0
IADR[23:16] Bits 23 through 16 of the address
controller is intended will require
32 bits of address. Therefore,
whenever
IADR[31:24] bits will be append-
ed to the 24-bit initialization ad-
dress, to each 24-bit descriptor
base address, and to each be-
ginning 24-bit buffer address in
order to form complete 32-bit ad-
dresses. The upper 8 bits that
exist in the descriptor address
registers and the buffer address
registers which are stored on
board the Am79C978A control-
ler will be overwritten with the
IADR[31:24] value, so that CSR
accesses to these registers will
show the 32-bit address that
includes the appended field.
If SSIZE32 = 1, then software will
provide 32-bit pointer values for
all of the shared software struc-
tures – i.e., descriptor bases and
buffer addresses, and therefore,
IADR[31:24] will not be written to
the upper 8 bits of any of these
resources, but it will be used as
the upper 8 bits of the initializa-
tion address.
This register is aliased with
CSR17.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or by setting the
STOP bit.
of the Initialization Block. When-
ever this register is written,
CSR17 is updated with CSR2's
contents.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or by setting the
STOP bit.
SSIZE32 = 0,
the