AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 38

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

38
Figure 11. Address Parity Error Response
DEVSEL
FRAME
SERR
C/BE
CLK
PAR
AD
1
DEVSEL
FRAME
2
PERR
TRDY
C/BE
IRDY
PAR
CLK
AD
ADDR
CMD
Figure 12. Slave Cycle Data Parity Error Response
3
1
PAR
4
2
1st DATA
BE
ADDR
CMD
22399A-14
PAR
3
5
PAR
Am79C978A
4
5
DATA
BE
During the data phase of an I/O write, memory-mapped
I/O write, or configuration write command that selects
the Am79C978A controller as target, the device sam-
ples the AD[31:0] and C/BE[3:0] lines for parity on the
clock edge, and data is transferred as indicated by the
assertion of IRDY and TRDY. PAR is sampled in the fol-
lowing clock cycle. If a parity error is detected and re-
porting of that error is enabled by setting PERREN
(PCI Command register, bit 6) to 1, PERR is asserted
one clock later. The parity error will always set PERR
(PCI Status register, bit 15) to 1 even when PERREN
is cleared to 0. The Am79C978A controller will finish a
transaction that has a data parity error in the normal
way by asserting TRDY. The corrupted data will be writ-
ten to the addressed location.
Figure 12 shows a transaction that suffered a parity
error at the time data was transferred (clock 7, IRDY
and TRDY are both asserted). PERR is driven high at
the beginning of the data phase and then drops low due
to the parity error on clock 9, two clock cycles after the
data was transferred. After PERR is driven low, the
Am79C978A controller drives PERR high for one clock
cycle, since PERR is a sustained tri-state signal.
6
PAR
7
8
9
10
22399A-15