AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 101

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

0
PCI Status Register
Offset 06h
The PCI Status register is a 16-bit register that contains
status information for the PCI bus related events. It is
located at offset 06h in the PCI Configuration Space.
Bit
15
IOEN
Name
PERR
before
Am79C978A controller will only
respond to accesses to the Ex-
pansion
ROMEN (PCI Expansion ROM
Base Address register, bit 0) and
MEMEN are set to 1. Since ME-
MEN also enables the memory
mapped
Am79C978A I/O resources, the
PCI Memory Mapped I/O Base
Address register must be pro-
grammed with an address so that
the device does not claim cycles
not intended for it.
MEMEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
IOEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
The Am79C978A controller sam-
ples the AD[31:0], C/BE[3:0], and
the PAR lines for a parity error at
the following times:
• In slave mode, during the ad-
dress phase of any PCI bus
command.
• In slave mode, for all I/O, mem-
ory, and configuration write com-
mands
Am79C978A
I/O Space Access Enable. The
Am79C978A controller will ignore
all I/O accesses when IOEN is
cleared. The host must set IOEN
before the first I/O access to the
device. The PCI I/O Base Ad-
dress register must be pro-
grammed with a valid I/O address
before setting IOEN.
Description
Parity Error. PERR is set when
the
detects a parity error.
Am79C978A
setting MEMEN. The
ROM
that
access
controller
select
when
to
controller
when
both
Am79C978A
the
the
14
13
12
SERR
RMABORT Received Master Abort. RM-
RTABORT
data is transferred (TRDY and
IRDY are asserted).
In master mode, during the data
phase
commands.
In master mode, during the data
phase of the memory write com-
mand, the Am79C978A controller
sets the PERR bit if the target re-
ports a data parity error by
asserting the PERR signal.
PERR is not effected by the state
of the Parity Error Response en-
able bit (PCI Command register,
bit 6).
PERR is set by the Am79C978A
controller and cleared by writing a
1. Writing a 0 has no effect.
PERR is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
when the Am79C978A controller
detects an address parity error
and both SERREN and PERREN
(PCI Command register, bits 8
and 6) are set.
SERR is set by the Am79C978A
controller and cleared by writing a
1. Writing a 0 has no effect.
SERR is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
ABORT
Am79C978A
nates a master cycle with a mas-
ter abort sequence.
RMABORT
Am79C978A
cleared by writing a 1. Writing a 0
has no effect. RMABORT is
cleared by H_RESET and is not
affected by S_RESET or by
setting the STOP bit.
ABORT is set when a target ter-
minates an Am79C978A master
cycle
sequence.
Signaled SERR. SERR is set
Received
with
of
is
Target
all
is
a
set
controller
controller
memory
set
target
Abort.
when
by
termi-
abort
read
101
and
RT-
the
the