AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 157

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

2-0
BCR19: EEPROM Control and Status
Bit
31-16 RES
15
PHYSEL [1:0]
Table 38.
LINBC
PVALID
00
01
10
11
Name
Expansion ROM/Flash
EADI/Internal MII Snoop
Reserved
Reserved
PHY Select Programming
These bits are read accessible al-
ways, these bits can only be writ-
ten from the EEPROM unless a
write-enable bit, BCR2[13], is set.
PHYSEL [1:0] is cleared by
H_RESET and is not affected by
S_RESET or STOP.
Reserved locations. These bits
are read accessible always; write
accessible only when either the
STOP or the SPND bit is set. Af-
ter H_RESET, the value in these
bits will be 001b. The setting of
these bits have no effect on any
Am79C978A controller’s func-
tion. LINBC is not affected by
S_RESET or STOP.
Reserved locations. Written as
zeros and read as undefined.
EEPROM Valid status bit. This bit
is read accessible only. PVALID
is read only; write operations
have no effect. A value of 1 in this
bit indicates that a PREAD opera-
tion has occurred, and that (1)
there is an EEPROM connected
to the Am79C978A controller in-
terface pins and (2) the contents
read from the EEPROM have
passed the checksum verification
operation.
A value of 0 in this bit indicates a
failure in reading the EEPROM.
The checksum for the entire 82
bytes of EEPROM is incorrect or
no EEPROM is connected to the
interface pins.
PVALID is set to 0 during
H_RESET and is unaffected by
S_RESET or the STOP bit. How-
ever, following the H_RESET op-
eration, an automatic read of the
Description
Mode
Am79C978A
14
PREAD
EEPROM will be performed. Just
as it is true for the normal PREAD
command, at the end of this auto-
matic read operation the PVALID
bit may be set to 1. Therefore,
H_RESET will set the PVALID bit
to 0 at first, but the automatic EE-
PROM read operation may later
set PVALID to a 1.
If PVALID becomes 0 following an
EEPROM read operation (either
automatically
H_RESET, or requested through
PREAD), then all EEPROM-pro-
grammable BCR locations will be
reset to their H_RESET values.
The content of the Address
PROM locations, however, will not
be cleared.
If no EEPROM is present at the
EESK, EEDI, and EEDO pins,
then
commands will terminate early
and PVALID will not be set.
This applies to the automatic
read of the EEPROM after
H_RESET, as well as to host-
initiated PREAD commands.
EEPROM Read command bit.
When this bit is set to a 1 by the
host, the PVALID bit (BCR19, bit
15) will immediately be reset to a
0, and then the Am79C978A con-
troller will perform a read opera-
tion
EEPROM through the interface.
The
fetched during the read will be
stored in the appropriate internal
registers on board the controller.
Upon completion of the EEPROM
read operation, the Am79C978A
controller will assert the PVALID
bit. EEPROM contents will be in-
directly accessible to the host
through read accesses to the Ad-
dress PROM (offsets 0h through
Fh) and through read accesses to
other EEPROM programmable
registers. Note that read access-
es from these locations will not
actually access the EEPROM it-
self, but instead will access the
Am79C978A internal copy of the
EEPROM
of
EEPROM
all
82
attempted
contents.
bytes
generated
data
from
PREAD
that
Write
after
157
the
is