AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 166

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

14
13-4
3-0
BCR30: Expansion Bus Data Port Register
Bit
31-16 RES
166
LAAINC
RES
EPADDRU
Name
SRAM cycle. For a complete de-
scription, see the section on Ex-
pansion Bus Accesses. This bit is
only applicable to reads or writes
to EBDATA (BCR30). It does not
affect Expansion ROM accesses
from the PCI system bus.
This bit is always read accessi-
ble; write accessible only when
the STOP bit is set. FLASH is 0
after H_RESET and is unaffected
by S_RESET or the STOP bit.
Lower Address Auto Increment.
When the LAAINC bit is set to 1,
the Expansion Port Lower Address
will automatically increment by one
after a read or write access to EB-
DATA (BCR30). When EBADDRL
reaches FFFFh and LAAINC is set
to 1, the Expansion Port Lower Ad-
dress (EPADDRL) will roll over to
0000h. When the LAAINC bit is set
to 0, the Expansion Port Lower Ad-
dress will not be affected in any
way after an access to EBDATA
(BCR30)
grammed.
This bit is always read accessi-
ble; write accessible only when
the STOP bit is set. LAINC is 0 af-
ter H_RESET and is unaffected
by S_RESET or the STOP bit.
Reserved locations. Written as
zeros and read as undefined.
Expansion Port Address Upper.
This upper portion of the Expan-
sion Bus address is used to pro-
vide addresses for Flash/EPROM
port accesses.
This bit is always read accessi-
ble; write accessible only when
the STOP bit is set or when
SRAM SIZE (BCR25, bits 7-0) is
0. EPADDRU is undefined after
H_RESET and is unaffected by
S_RESET or the STOP bit.
Reserved locations. Written as
zeros and read as undefined.
Description
and
must
be
Am79C978A
pro-
15-0
EBDATA
Expansion Bus Data Port. EBDATA
is the data port for operations on the
Expansion Port accesses involving
SRAM and Flash accesses. The
type of access is set by the FLASH
bit (BCR 29, bit 15). When the
FLASH bit is set to 1, the Expansion
Bus access will follow the Flash ac-
cess timing. When the FLASH bit is
set to 0, the Expansion Bus access
will follow the SRAM access timing.
Note: It is important to set the
FLASH bit and load Expansion
Port Address EPADDR (BCR28,
BCR29) with the required ad-
dress before attempting read or
write to the Expansion Bus data
port. The Flash and SRAM ac-
cesses use different address
phases. Incorrect configuration
will result in a possible corruption
of data.
Flash read cycles are performed
when BCR30 is read and the
FLASH bit (BCR29, bit 15) is set
to 1. Upon completion of the read
cycle, the 8-bit result for Flash ac-
cess is stored in EBDATA[7:0],
EBDATA[15:8]
Flash write cycles are performed
when BCR30 is written and the
FLASH bit (BCR29, bit 15) is set
to 1. EBDATA[7:0] only is valid
for write cycles.
SRAM read cycles are performed
when BCR30 is read and the
FLASH bit (BCR29, bit 15) is set
to 0. Upon completion of the read
cycle, the 16-bit result for SRAM
access is stored in EBDATA.
Write cycles to the SRAM are in-
voked when BCR30 is written
and the FLASH bit (BCR29, bit
15) is set to 0. Byte writes to the
SRAM must use a read-modify-
write scheme since the word is al-
ways valid for SRAM write or
read accesses.
This bit is read and write accessi-
ble only when the STOP is set or
when SRAM SIZE (BCR25, bits
7-0) is 0. EBDATA is undefined
after H_RESET and is unaffected
by S_RESET and the STOP bit.
is
undefined.