AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 111

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

6
5
4
3
IENA
RXON
TXON
TDMD
This bit is always read accessi-
ble. INTR is read only. INTR is
cleared by clearing all of the ac-
tive individual interrupt bits that
have not been masked out.
This bit is always read/write ac-
cessible. IENA is set by writing
a 1 and cleared by writing a 0.
IENA is cleared by H_RESET or
S_RESET
STOP bit.
This bit is always read accessi-
ble. RXON is read only. RXON
is cleared by H_RESET or
S_RESET
STOP bit.
This bit will reset if the DXSUF-
LO bit (CSR3, bit 6) is reset and
there is an underflow condition
encountered.
Read accessible always. TXON
is read only. TXON is cleared by
H_RESET or S_RESET and
setting the STOP bit.
Interrupt Enable allows INTA to
be active if the Interrupt Flag is
set. If IENA = 0, then INTA will
be disabled regardless of the
state of INTR.
Receive On indicates that the re-
ceive function is enabled. RXON
is set if DRX (CSR15, bit 0) is set
to 0 after the START bit is set. If
INIT and START are set together,
RXON will not be set until after
the initialization block has been
read in.
Transmit On indicates that the
transmit function is enabled.
TXON is set if DTX (CSR15, bit 1)
is set to 0 after the START bit is
set. If INIT and START are set to-
gether, TXON will not be set until
after the initialization block has
been read in.
Transmit Demand, when set,
causes the Buffer Management
Unit to access the Transmit De-
scriptor Ring without waiting for
the poll-time counter to elapse. If
TXON is not enabled, TDMD bit
and
and
setting
setting
Am79C978A
the
the
2
1
0
STOP
STRT
INIT
will be reset and no Transmit De-
scriptor Ring access will occur.
TDMD is required to be set if the
TXDPOLL bit in CSR4 is set.
Setting
TXDPOLL = 0 merely hastens
the controller’s response to a
Transmit Descriptor Ring Entry.
This bit is always read/write ac-
cessible. TDMD is set by writing
a 1. Writing a 0 has no effect.
TDMD will be cleared by the
Buffer Management Unit when it
fetches a Transmit Descriptor.
TDMD is cleared by H_RESET
or S_RESET and setting the
STOP bit.
chip from all DMA activity. The
chip remains inactive until either
STRT or INIT are set. If STOP,
STRT, and INIT are all set to-
gether,
STRT and INIT.
This bit is always read/write ac-
cessible. STOP is set by writing
a 1, by H_RESET or S_RESET.
Writing a 0 has no effect. STOP
is cleared by setting either
STRT or INIT.
Am79C978A controller to send
and receive frames and perform
buffer management operations.
Setting STRT clears the STOP
bit. If STRT and INIT are set to-
gether, the Am79C978A control-
ler initialization will be performed
first.
This bit is always read/write ac-
cessible. STRT is set by writing
a 1. Writing a 0 has no effect.
STRT is cleared by H_RESET,
S_RESET, or by setting the
STOP bit.
Am79C978A controller to begin
the initialization procedure which
reads in the initialization block
from memory. Setting INIT clears
the STOP bit. If STRT and INIT
are set together, the Am79C978A
STOP assertion disables the
STRT assertion enables the
INIT
assertion
STOP
TDMD
will
enables
override
while
111
the