AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 160

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

1
BCR20: Software Style
This register is an alias of the location CSR58. Accesses
to and from this register are equivalent to accesses to
CSR58.
Bit
31-11 RES
160
0
ESK
EDI/EDO
Name
EEPROM Serial Clock. This bit and
the EDI/EDO bit are used to control
host access to the EEPROM. Val-
ues programmed to this bit are
placed onto the EESK pin at the ris-
ing edge of the next clock following
bit programming, except when the
PREAD bit is set to 1 or the EEN bit
is set to 0. If both the ESK bit and
the
changed during one BCR19 write
operation, while EEN = 1, then set-
up and hold times of the EEDI pin
value with respect to the EESK sig-
nal edge are not guaranteed.
ESK has no effect on the EESK
pin unless the PREAD bit is set to
0 and the EEN bit is set to 1.
This bit is read accessible al-
ways, write accessible only when
either the STOP or the SPND bit
is set. ESK is reset to 1 by
H_RESET and is not affected by
S_RESET or STOP.
Data Out. Data that is written to
this bit will appear on the EEDI
output of the interface, except
when the PREAD bit is set to 1 or
the EEN bit is set to 0. Data that
is read from this bit reflects the
value of the EEDO input of the
interface.
EDI/EDO has no effect on the
EEDI pin unless the PREAD bit
is set to 0 and the EEN bit is set
to 1.
Read accessible always; write
accessible only when either the
STOP or the SPND bit is set. EDI/
EDO is reset to 0 by H_RESET
and is not affected by S_RESET
or STOP.
Reserved locations. Written as
zeros and read as undefined.
EEPROM
Description
EDI/EDO
Data
bit
In/EEPROM
values
Am79C978A
are
10
9
8
APERREN
RES
SSIZE32
Reserved location. Written as zero;
Software Size 32 bits. When set,
Advanced Parity Error Handling
Enable. When APERREN is set
to 1, the BPE bits (RMD1 and
TMD1, bit 23) start having a
meaning. BPE will be set in the
descriptor associated with the
buffer that was accessed when a
data parity error occurred. Note
that since the advanced parity er-
ror handling uses an additional bit
in the descriptor, SWSTYLE (bits
7-0 of this register) must be set to
2
Am79C978A controller to use 32-
bit software structures.
APERREN does not affect the re-
porting of address parity errors or
data parity errors that occur when
the Am79C978A controller is the
target of the transfer.
Read anytime; write accessible
only when either the STOP or the
SPND bit is set. APERREN is
cleared by H_RESET and is not
affected by S_RESET or STOP.
read as undefined.
this
Am79C978A controller utilizes
32-bit software structures for the
initialization block and the trans-
mit and receive descriptor en-
tries. When cleared, this bit
indicates that the Am79C978A
controller utilizes 16-bit software
structures for the initialization
block and the transmit and re-
ceive descriptor entries. In this
mode, the Am79C978A controller
is backwards compatible with the
Am7990 LANCE and Am79C960
PCnet-ISA controllers.
The value of SSIZE32 is deter-
mined by the Am79C978A con-
troller according to the setting of
the Software Style (SWSTYLE,
bits 7-0 of this register).
This bit is always read accessible.
SSIZE32 is read only; write opera-
tions will be ignored. SSIZE32 will
be cleared after H_RESET (since
SWSTYLE defaults to 0) and is
or
bit
3
indicates
to
program
that
the
the