AM79C978A AMD [Advanced Micro Devices], AM79C978A Datasheet - Page 133

• Manufacturer Part Number: AM79C978A
• Description: Single-Chip 1/10 Mbps PCI Home Networking Controller
• Manufacturer: AMD [Advanced Micro Devices]

CSR60: Previous THd3nsmit Descriptor Address
Lower
Bit
31-16 RES
15-0
CSR61: Previous Transmit Descriptor Address
Upper
Bit
31-16 RES
15-0
SWSTYLE
All Other
PXDAL
PXDAU
Name
Name
[7:0]
00h
01h
02h
03h
Reserved locations. Written as
zeros and read as undefined.
Contains the lower 16 bits of the
previous transmit descriptor ad-
dress pointer. The Am79C978A
controller has the capability to
stack multiple transmit frames.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Reserved locations. Written as
zeros and read as undefined.
Contains the upper 16 bits of the
previous transmit descriptor ad-
dress pointer. The Am79C978A
controller has the capability to
stack multiple transmit frames.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Description
Description
LANCE/PCnet-ISA
controller
RES
PCnet-PCI
controller
PCnet-PCI
controller
RES
Name
Style
Table 32. Software Styles
Undefined
SSIZE32
Am79C978A
0
1
1
1
CSR62: Previous Transmit Byte Count
Bit
31-16 RES
15-12 RES
11-0
CSR63: Previous Transmit Status
Bit
31-16 RES
15-0
16-bit software structures,
non-burst or burst access
RES
32-bit software structures,
non-burst or burst access
32-bit software structures,
non-burst or burst access
Undefined
Initialization Block
PXBC
NameDescription
PXST
Name
Entries
Reserved locations. Written as
Reserved locations. Written as
Previous Transmit Status. This
zeros and read as undefined.
Reserved locations.
Previous Transmit Byte Count.
This field is a copy of the BCNT
field of TMD1 of the previous
transmit descriptor.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
zeros and read as undefined.
field is a copy of bits 31-16 of
TMD1 of the previous transmit
descriptor.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Description
16-bit software structures,
non-burst access only
RES
32-bit software structures,
non-burst access only
32-bit software structures,
non-burst or burst access
Undefined
Descriptor Ring Entries
133